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rev. 4265a?aero?07/03 1 features ee programmable 1,048,576 x 1-bit serial memory designed to store configuration programs for field programmable gate arrays (fpgas) very low-power cmos eeprom process in-system programmable (isp) via two-wire bus simple interface to sram fpgas compatible with at40k devices cascadable read-back to support additional configurations or higher-density arrays programmable reset polarity low-power standby mode high-reliability ? endurance: 100,000 write cycles batch tested for 10 krads tid and 70 mev latch up capability operating range: 3.0v to 3.6v, -55c to +125c available in 400 mils wide 28 pins dil flat pack description the AT17LV010-10DP is a fpga configuration eeprom provides an easy-to-use, cost-effective configuration memory for field programmable gate arrays. it is pack- aged in the 28-pin 400 mils wide fp package. configurator uses a simple serial- access procedure to configure one or more fpga devices. the user can select the polarity of the reset function by programming four eeprom bytes. the device also supports a write-protection mechanism within its programming mode. space fpga configuration eeprom at17lv010- 10dp advance information rev. 4265a?aero?07/03
2 a717lv010-10dp 4265a?aero?07/03 pin configuration figure 1. 28-pin flat pack 1 2 3 4 5 6 7 8 9 10 reset/oe nc wp2 ce gnd nc nc nc nc nc nc wp1 clk data nc nc nc nc vcc 28 27 26 23 22 21 20 19 18 17 16 nc ce0 nc nc ready 15 24 25 nc nc ser_en nc
3 a717lv010-10dp 4265a ? aero ? 07/03 block diagram device description the control signals for the configuration eeprom (ce , reset/oe and cclk) inter- face directly with the fpga device control signals. all fpga devices can control the entire configuration process and retrieve data from the configuration eeprom without requiring an external intelligent controller. the configuration eeprom reset/oe and ce pins control the tri-state buffer on the data output pin and enable the address counter. when reset/oe is driven high, the configuration eeprom resets its address counter and tri-states its data pin. the ce pin also controls the output of the AT17LV010-10DP configurator. if ce is held high after the reset/oe reset pulse, the counter is disabled and the data output pin is tri- stated. when oe is subsequently driven low, the counter and the data output pin are enabled. when reset/oe is driven high again, the address counter is reset and the data output pin is tri-stated, regardless of the state of ce . when the configurator has driven out all of its data and ceo is driven low, the device tri-states the data pin to avoid contention with other configurators. upon power-up, the address counter is automatically reset. this is the default setting for the device. since almost all fpgas use reset low and oe high, this document will describe reset /oe. power on reset ser_en wp1 wp2 ready
4 a717lv010-10dp 4265a ? aero ? 07/03 pin description data tri-state data output for configuration. open-collector bi-directional pin for programming. clk clock input. used to increment the internal address and bit counter for reading and programming. wp1 write protect (1). used to protect portions of memory during programming. dis- abled by default due to internal pull-down resistor. this input pin is not used during fpga loading operations. reset/oe output enable (active high) and reset (active low) when ser_en is high. a low level on reset /oe resets both the address and bit counters. a high level (with ce low) enables the data output driver. the logic polarity of this input is programmable as either reset/oe or reset /oe. for most applications, reset should be programmed active low. this document describes the pin as reset /oe. wp2 write protect (2). used to protect portions of memory during programming. dis- abled by default due to internal pull-down resistor. this input pin is not used during fpga loading operations. ce chip enable input (active low). a low level (with oe high) allows clk to increment the address counter and enables the data output driver. a high level on ce disables both the address and bit counters and forces the device into a low-power standby mode. note that this pin will not enable/disable the device in the two-wire serial programming mode (ser_en low). gnd ground pin. a 0.2 f decoupling capacitor between v cc and gnd is recommended. ceo chip enable output (active low). this output goes low when the address counter has reached its maximum value. in a daisy chain of AT17LV010-10DP devices, the ceo pin of one device must be connected to the ce input of the next device in the chain. it will stay low as long as ce is low and oe is high. it will then follow ce until oe goes low; thereafter, ceo will stay high until the entire eeprom is read again. a2 device selection input, a2. this is used to enable (or select) the device during program- ming (i.e., when ser_en is low). a2 has an internal pull-down resistor. ready open collector reset state indicator. driven low during power-up reset, released when power-up is complete. it is recommended to use a 4.7 k ? pull-up resistor when this pin is used. ser_en serial enable must be held high during fpga loading operations. bringing ser_en low enables the two-wire serial programming mode. for non-isp applications, ser_en should be tied to v cc . v cc 3.3v (0.3v).
5 a717lv010-10dp 4265a ? aero ? 07/03 fpga master serial mode summary the i/o and logic functions of any sram-based fpga are established by a configura- tion program. the program is loaded either automatically upon power-up, or on command, depending on the state of the fpga mode pins. in master mode, the fpga automatically loads the configuration program from an external memory. the at17lv serial configuration eeprom has been designed for compatibility with the master serial mode. this document discusses the atmel at40kel applications. control of configuration most connections between the fpga device and the at17lv serial eeprom are sim- ple and self-explanatory. the data output of the AT17LV010-10DP configurator drives din of the fpga devices. the master fpga cclk output drives the clk input of the AT17LV010-10DP configurator. the ceo output of any AT17LV010-10DP configurator drives the ce input of the next configurator in a cascaded chain of eeproms. ser_en must be connected to v cc (except during isp). the ready pin is available as an open-collector indicator of the device ? s reset status; it is driven low while the device is in its power-on reset cycle and released (tri-stated) when the cycle is complete. cascading serial configuration eeproms for multiple fpgas configured as a daisy-chain, or for fpgas requiring larger configu- ration memories, cascaded configurators provide additional memory. after the last bit from the first configurator is read, the clock signal to the configurator asserts its ceo output low and disables its data line driver. the second configurator recognizes the low level on its ce input and enables its data output. after configuration is complete, the address counters of all cascaded configurators are reset if the reset /oe on each configurator is driven to its active (low) level. if the address counters are not to be reset upon completion, then the reset /oe input can be tied to its inactive (high) level. reset pat17lv010- 10dpolarity the AT17LV010-10DP configurator allows the user to program the reset polarity as either reset/oe or reset /oe. this feature is supported by industry-standard pro- grammer algorithms. programming mode the programming mode is entered by bringing ser_en low. in this mode the chip can be programmed by the two-wire serial bus. the programming is done at v cc supply only. programming super voltages are generated inside the chip. standby mode the AT17LV010-10DP configurator enter a low-power standby mode whenever ce is asserted high. in this mode, the AT17LV010-10DP configurator consumes less than 100 a of current at 3.3v. the output remains in a high-impedance state regardless of the state of the oe input.
6 a717lv010-10dp 4265a ? aero ? 07/03 dc characteristics v cc = 3.3v 0.3v electrical characteristics absolute maximum ratings* operating temperature.................................. -55 c to +125 c *notice: stresses beyond those listed under absolute maximum ratings may cause permanent dam- age to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond those listed under oper- ating conditions is not implied. exposure to abso- lute maximum rating conditions for extended periods of time may affect device reliability. storage temperature ..................................... -65 c to +150 c voltage on any pin with respect to ground ..............................-0.1v to v cc +0.5v supply voltage (v cc ) .........................................-0.5v to +7.0v maximum soldering temp. (10 sec. @ 1/16 in.).............260 c esd (r zap = 1.5k, c zap = 100 pf)................................. 2000v operating conditions symbol description 3.3v units min max v cc military -55 to +125 c3.03.6v symbol description AT17LV010-10DP units min max v ih high-level input voltage 2.0 v cc v v il low-level input voltage 0 0.8 v v oh high-level output voltage (i oh = -2.5 ma) 2.4 v v ol low-level output voltage (i ol = +3 ma) 0.4 v i cca supply current, active mode 10 ma i l input or output leakage current (v in = v cc or gnd) -10 10 a i ccs supply current, standby mode 200 a
7 a717lv010-10dp 4265a ? aero ? 07/03 ac characteristics ac characteristics when cascading ce reset/oe clk data t sce t lc t hc t cac t oe t ce t oh t hoe t sce t hce t df t oh ce reset/oe clk data ceo t cdf t ock t oce t oce t ooe last bit first bit
8 a717lv010-10dp 4265a ? aero ? 07/03 ac characteristics v cc = 3.3v 0.3v notes: 1. ac test lead = 50 pf. 2. float delays are measured with 5 pf ac loads. transition is measured 200 mv from steady-state active levels. ac characteristics when cascading v cc = 3.3v 0.3v notes: 1. ac test lead = 50 pf. 2. float delays are measured with 5 pf ac loads. transition is measured 200 mv from steady-state active levels. symbol description military units min max t oe (1) oe to data delay 55 ns t ce (1) ce to data delay 60 ns t cac (1) clk to data delay 60 ns t oh data hold from ce , oe, or clk 0 ns t df (2) ce or oe to data float delay 50 ns t lc clk low time 25 ns t hc clk high time 25 ns t sce ce setup time to clk (to guarantee proper counting) 35 ns t hce ce hold time from clk (to guarantee proper counting) 0ns t hoe oe high time (guarantees counter is reset) 25 ns f max maximum clock frequency 10 mhz symbol description military units min max t cdf (2) clk to data float delay 50 ns t ock (1) clk to ceo delay 55 ns t oce (1) ce to ceo delay 40 ns t ooe (1) reset /oe to ceo delay 40 ns f max maximum clock frequency 10 mhz
9 a717lv010-10dp 4265a ? aero ? 07/03 ordering information memory size ordering code package operation range 1 mbit AT17LV010-10DP-e 28-pin flat pack engineering samples 1 mbit AT17LV010-10DP-m 28-pin flat pack standard mil. temperature 1 mbit AT17LV010-10DP-mq 28-pin flat pack qml q 1 mbit AT17LV010-10DP-sv 28-pin flat pack qml v
10 a717lv010-10dp 4265a ? aero ? 07/03 packaging information dp (fp28.4)
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